The present invention relates to a magnetic random access memory circuit (called a "MRAM circuit" in this specification).
A magnetic random access memory includes a plurality of memory cells located at intersections of word lines and bit lines, each memory cell being basically constituted of a pair of ferromagnetic layers separated by an insulating or non-magnetic metal layer. Digital information is represented by the direction of magnetic vectors in the ferromagnetic layers, and is infinitely maintained unless it is intentionally rewritten. In order to write or change the state of the memory cell, a composite magnetic field which is generated by use of a word current and a bit current and which is larger than a threshold, is applied to the memory cell, so as to reverse the magnetization of the ferromagnetic layers.
A first example of the magnetic random access memory includes a number of memory cells configured to utilize a giant magneto-resistive (GMR) effect, as disclosed by U.S. Pat. No. 5,748,519 and IEEE Transaction On Components Packaging and Manufacturing Technology--Part A Vol. 170, No. 3, pp373-379 (the content of which are incorporated by reference in its entirety into this application). Referring to FIG. 1, there is shown a layout diagram of a simplified MRAM circuit including each memory cell configured to utilize the GMR effect. As shown in FIG. 1, the MRAM circuit includes a memory array divided into a first array portion 604 and a second array portion 605, a decoder consisting of a row decoder 602 and a column decoder 603, and a comparator 606. The row decoder 602 and the column decoder 603 are connected to an address bus 601, respectively. In a reading operation, one of the first array portion 604 and the second array portion 605 is used as a reference cell.
In this first prior art example, separate word lines are required for a memory cell and a reference cell, respectively, and a memory cell array and a reference cell array are separated or put apart from each other. Therefore, a reference signal is inclined to contain a parasite component, with the result that it is difficult to have a sufficient margin in operation. Accordingly, a high level of equality in characteristics is required for memory cells on the same wafer. In addition, since the separate word lines are required for a memory cell and a reference cell, respectively, and since the memory cell array and the reference cell array are separated apart from each other, a memory cell area is large, so that it is difficult to elevate the integration density for microminiaturization.
Furthermore, in this first prior art example, since two cells (one included in the first array portion 604 and another included in the second array portion 605) are required for one address, a memory cell area is large, so that it is difficult to elevate the integration density for microminiaturization.
A second example of the magnetic random access memory includes a number of memory cells configured to utilize a magnetic tunnel junction (MTJ) effect, as disclosed by U.S. Pat. No. 5,640,343 (the content of which is incorporated by reference in its entirety into this application). Referring to FIG. 2, there is shown a MRAM circuit including each memory cell configured to utilize the MTJ effect. The shown MRAM circuit includes row decoders 701 and 702, column decoders 703 and 704, and a matrix circuit having a number of MTJ elements 711 to 715 and so on located at intersections of word lines 705, 706 and 707 extending between the row decoders 701 and 702 and bit lines 708, 709 and 710 extending between the column decoders 703 and 704. In this MRAM circuit, a stored information is distinguished dependent upon whether a sense current is large or small. However, this patent does not disclose a method for detecting the magnitude (large or small) of the sense current, nor does it show how to connect a comparator (sense amplifier).